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Control-Oriented Mathematical Review of a 24 V-to-19 V PWM Buck Converter: State-Space Averaging, CCM Boundary, Type-III Loop Compensation and Design Consistency

1. Shiaondo Kenneth Chia
2. Gbaden Amenger
3. N. Y. Goshwe

Volume 1, Issue 2 · Pioneer Volume · August 2026 · Part 2 · e049 · ISSN pending assignment

CHIATECH JOURNAL

SETEHEM · Volume 1, Issue 2 · Pioneer Volume · August 2026 · Part 2 · e049

PIONEER PUBLICATION · ACCEPTED ARTICLE · THEORETICAL ENGINEERING REVIEW · POWER ELECTRONICS · CONTROL SYSTEMS · MATHEMATICAL RE-ANALYSIS

Control-Oriented Mathematical Review of a 24 V-to-19 V PWM Buck Converter: State-Space Averaging, CCM Boundary, Type-III Loop Compensation and Design Consistency

CHIA, Shiaondo Kenneth¹* · AMENGER, Gbaden² · GOSHWE, N. Y.³

¹ CHIA TECH Solutions and Resources Limited, Nigeria; original project investigator, Department of Electrical/Electronic Engineering, Federal University of Agriculture Makurdi (2016)

² Nigeria Customs Service, Ogun State Command, Nigeria; original project investigator, Department of Electrical/Electronic Engineering, Federal University of Agriculture Makurdi (2016)

³ Department of Electrical/Electronic Engineering, Federal University of Agriculture Makurdi, Nigeria; project supervisor (2016)

*Corresponding author: chiakenneth01@gmail.com · ORCID: https://orcid.org/0009-0009-6434-4586

Abstract

Background: The archived 2016 project designed, simulated and implemented a 24 V-to-19 V voltage-mode PWM buck converter at 30 kHz using a 251 µH inductor, 15 µF output capacitor, 10 mΩ capacitor ESR and 2 mΩ inductor DCR. Its control design selected a 6 kHz crossover target, 60° desired phase margin and a Type-III compensator through a K-factor procedure. Objective: This paper provides a theory-centred re-analysis of the same converter, preserving the source record while reconstructing its switch-state equations, state-space averaged model, small-signal duty-to-output dynamics, CCM/DCM boundary, frequency landmarks and Type-III phase budget. It also audits mathematical inconsistencies that become visible when the archived equations are recomputed. Methods: Ideal CCM switching equations were averaged and linearized around the documented operating point. The rated 3.5 A condition was treated as the principal load case (R = 19/3.5 = 5.43 Ω), while the independently documented 5 Ω schematic load was retained as a separate source branch. Bode response, phase budget and K-factor sensitivity were computed analytically. Results: The ideal duty ratio is 0.7917, Ton = 26.39 µs and Toff = 6.94 µs. The formula-consistent inductor ripple is 0.526 A p-p, giving a CCM boundary current of about 0.263 A and Rcrit ≈ 72.3 Ω. The LC double-pole frequency is 2.594 kHz and the ESR zero is approximately 1.06 MHz. At the archived 6 kHz crossover, the ideal power-stage phase is approximately −158.2°. A 60° phase-margin target therefore requires about +38.2° compensator phase at crossover; when the Type-III integrator’s −90° baseline is included, the two lead sections must supply about 128.2° of lead, corresponding to K ≈ 18.9. The archived 150° boost gives K ≈ 57.7 and is therefore conservative but highly sensitive. The historical report also contains two explicit consistency issues: 3.5 A at 19 V implies 5.43 Ω rather than 5 Ω, and the displayed ripple equation uses Vout while its numerical substitution uses 24 V. Conclusion: The converter is theoretically coherent at the topology and loop-design level, but a modern publication benefits from separating the PWM modulator gain from LC-plant phase, distinguishing parallel source load cases and documenting arithmetic substitutions. The resulting framework is a stronger theoretical basis for simulation, frequency-response verification and future hardware replication.

Keywords: buck converter; state-space averaging; small-signal model; voltage-mode control; Type-III compensation; K-factor; CCM; Bode plot; phase margin; power electronics

1. Introduction

A technically mature buck-converter paper should connect four levels of description: the actual ON/OFF switching circuit, an averaged large-signal model, a linear small-signal model for frequency-domain reasoning, and a closed-loop compensator design. The archived project contains all four ideas, but they are distributed across topology discussion, design equations, MATLAB/Simulink work and K-factor compensation calculations. e049 consolidates those ideas into a control-oriented mathematical framework rather than presenting another empirical result set.

The archival record is strong enough to support a source-constrained re-analysis. It documents 24 V input, 19 V output, 3.5 A rated current, 66.5 W output, 30 kHz switching, 251 µH inductance, 15 µF capacitance, 10 mΩ capacitor ESR and 2 mΩ inductor DCR. It also records a voltage-mode control architecture and Type-III compensation. However, two details should remain explicit rather than harmonized silently: the schematic/table also uses a 5 Ω load, and one inductor-ripple numerical substitution uses 24 V although the displayed equation is written in terms of Vout. These are treated as theoretical-review findings, not as grounds for discarding the genuine project evidence.

Figure 1. Four-layer mathematical interpretation used in e049. The archived project supplies the design point and compensation targets; the averaged and small-signal models are reconstructed analytically from those parameters.

2. Evidence Boundary and Theoretical Method

Table 1. Source-constrained baseline. e049 does not infer undocumented hardware measurements or silently collapse the 3.5 A and 5 Ω load statements into one value.

Contemporary control literature supports state-space averaging as a standard route from switched converter equations to control-oriented small-signal models. For voltage-mode buck control, the modulator contributes a gain set by the ramp amplitude while the LC filter contributes the dominant second-order phase lag; Type-III compensation supplies an integrator, two zeros and two additional high-frequency poles to recover phase and shape crossover (Khan et al., 2024; Analog Devices, n.d.-a, n.d.-b).

3. Switching and Averaged Mathematical Model

3.1 Steady-state conversion and switching intervals

For the ideal buck converter in continuous conduction mode, volt-second balance on the inductor gives the familiar conversion ratio

These values reproduce the archived rounded 26 µs ON and 7 µs OFF intervals. The large duty ratio also explains why the freewheel interval is short but non-negligible.

3.2 ON/OFF differential equations

With state vector x = [iL, vo]ᵀ and a resistive load R, the idealized ON and OFF dynamics are

Figure 2. Switching-state interpretation and resulting triangular inductor current. The output capacitor smooths the difference between inductor current and load current.

3.3 State-space averaged model

Averaging over one switching period replaces the binary switch state with duty ratio d(t). For the ideal buck converter,

At equilibrium, d = D and the steady state returns Vo = DVin and IL = Vo/R. Small perturbations x = X + x̂ and d = D + d̂ lead directly to a duty-to-output model suitable for loop design.

4. CCM Boundary, Ripple and Load Consistency

4.1 Ripple and CCM/DCM boundary

At the rated 3.5 A operating point, Imin = 3.237 A, so the converter is comfortably inside CCM. The CCM boundary occurs near 0.263 A average load current, far below the rated current. The estimated capacitor-only triangular ripple is 146.0 mV p-p and the 10 mΩ ESR adds about 5.3 mV p-p under this idealized calculation; layout, switching edges and device parasitics are not represented.

Figure 3. CCM/DCM boundary from the reconstructed ripple current. Rated operation has a wide current margin above the boundary.

4.2 The 3.5 A versus 5 Ω load statements

The rated current and output voltage imply R = Vo/Io = 19/3.5 = 5.43 Ω. The archived schematic and component table also show RL = 5 Ω, which would draw 3.8 A at 19 V and correspond to 72.2 W. Both statements are retained because the source supports both; e049 uses 5.43 Ω for the rated 66.5 W analysis and treats 5 Ω as a separate schematic-load condition. This distinction slightly changes damping and Q but does not alter the fundamental LC resonance.

5. Small-Signal Frequency Response and Type-III Compensation

5.1 LC pole, ESR zero and the archived crossover target

The ESR zero is more than 35 times the 30 kHz switching frequency and about 177 times the archived 6 kHz crossover target. Consequently, it has negligible phase impact around the intended loop bandwidth. This supports the original conclusion that the low-ESR output network needs substantial external phase compensation, but it also means a practical high-frequency compensator pole should primarily serve switching-noise roll-off rather than attempt to cancel a megahertz ESR zero below a 30 kHz switching ceiling.

Figure 4. Reconstructed ideal duty-to-output Bode response with and without the documented 10 mΩ ESR zero. At 6 kHz the ideal power-stage phase is approximately -158.2°; the ESR zero is too high to materially change the phase near crossover.

5.2 Phase-budget reconstruction

The archived calculation states a desired phase margin of 60° and assigns −180° to “modulator phase shift,” producing a required 150° phase boost after subtracting the Type-III integrator’s 90°. Modern voltage-mode partitioning is more precise: the PWM modulator is primarily a gain block, approximately Vin/Vsaw for a comparator/ramp implementation, while the LC power stage supplies the second-order phase lag. Using the archived 2 V sawtooth value gives a nominal modulator gain of 12, but the exact loop gain still depends on feedback scaling and error-amplifier transfer.

Figure 5. Phase-budget comparison. The archived 150° boost is conservative, but the modern decomposition attributes the high-frequency phase lag to the LC plant rather than to the PWM modulator itself.

5.3 K-factor sensitivity

The archived project used the classical K-factor expression

For 150° boost, the equation gives K = 57.7, reproducing the archived value. The reconstructed ideal-plant requirement of about 128.2° gives K ≈ 18.9. The difference is not a minor numerical adjustment: K rises rapidly as requested boost approaches 180°, so a conservative phase assumption materially changes the required pole-zero separation and component ratios.

Figure 6. K-factor sensitivity to requested Type-III phase boost. The nonlinearity explains why phase-partition assumptions should be documented explicitly.

5.4 Practical pole-zero placement logic

A voltage-mode Type-III network contains an integrator pole, two compensating zeros and two higher-frequency poles. Modern guidance places the zeros around the LC resonance to recover phase, then places high-frequency poles above the desired bandwidth to restore roll-off and attenuate switching noise. When a meaningful capacitor ESR zero lies within the control-relevant band, one high-frequency pole may be used to cancel it; that is not the case here because the documented ESR zero is approximately 1.06 MHz (Analog Devices, n.d.-a).

Figure 7. Frequency-separation map. The 2.594 kHz LC resonance and 6 kHz crossover dominate the useful loop-shaping range; the 1.06 MHz ESR zero lies far beyond switching frequency.

6. Mathematical Consistency Review of the Archived Design

The value of a theoretical review is not to rewrite the historical project into a cleaner story. It is to preserve the source and make its mathematical boundary explicit. Three findings are especially important. First, the ideal conversion ratio, switching intervals, LC frequency, ESR zero and the stated K = 57.7 all reproduce cleanly. Second, the rated-current load and the schematic 5 Ω load are different operating points. Third, the archived ripple derivation displays ΔiL = Vout(1−D)/(Lfs), but the numerical line substitutes 24 V rather than the displayed 19 V, producing approximately 0.657 A instead of the formula-consistent 0.526 A.

Figure 8. Source-versus-reanalysis consistency audit. Confirmed quantities are retained; ambiguous or inconsistent quantities are reported as such rather than silently “corrected.”

The phase calculation also benefits from updated terminology. Contemporary control references describe the buck loop as a modulator gain, an LC filter transfer function and a compensator transfer function. Thus the archived −180° quantity is better interpreted as a conservative estimate of uncompensated high-frequency plant phase rather than the phase shift of the PWM modulator alone (Analog Devices, n.d.-b). This reinterpretation preserves the design intent—obtain adequate phase margin at 6 kHz—while making the block-level mathematics consistent with modern control notation.

7. Engineering Implications and Validation Path

The theoretical reconstruction suggests three practical lessons. First, the power stage is intrinsically a second-order system with resonance near 2.6 kHz, so a 6 kHz crossover deliberately pushes beyond the LC pole and demands substantial phase recovery. Second, low ESR removes helpful ESR phase lead from the control band, strengthening the case for Type-III compensation. Third, the loop should be validated on hardware with a frequency-response analyzer or injection method because op-amp bandwidth, ramp amplitude, feedback divider, parasitic resistance, delay and actual capacitor/inductor values can shift gain and phase from the ideal model.

State-space averaging is particularly useful for control design because it produces a compact continuous model, but by construction it suppresses switching ripple. A modern validation package should therefore compare three views: the switched time-domain model for ripple and switching stress, the averaged model for large-signal dynamic reasoning, and the measured/small-signal Bode response for stability. Recent review literature similarly emphasizes state-space averaging as a control-oriented representation while noting that the averaged model does not reproduce switching ripple itself (Khan et al., 2024).

Figure 9. Theory-to-hardware validation chain for a future replication. The present paper makes no new measured hardware claims; it defines the mathematics that such a campaign should test.

8. Conclusion

This theoretical engineering review reconstructs the archived 24 V-to-19 V PWM buck converter from switching physics through averaged and small-signal models to Type-III loop compensation. The source-supported operating point gives D = 0.7917, Ton = 26.39 µs, Toff = 6.94 µs, ΔIL ≈ 0.526 A p-p, Iboundary ≈ 0.263 A, Rcrit ≈ 72.3 Ω, fLC = 2.594 kHz and fESR ≈ 1.06 MHz. At the archived fc = 6 kHz target, the ideal plant phase is about -158.2°, so a 60° phase-margin design requires approximately 128.2° of lead above the Type-III integrator baseline; the archived 150° / K = 57.7 choice is conservative but highly sensitive. The paper also identifies, without concealing, the 3.5 A versus 5 Ω load divergence and the 24 V substitution in an equation written for Vout. By separating source evidence, mathematical reconstruction and modern control interpretation, e049 converts the original project into a more rigorous, reproducible and publication-ready theoretical contribution.

Declarations

Authorship/provenance: The archived 2016 project file identifies Chia S. Kenneth as the student investigator and Goshwe N. Y. as supervisor. The attribution of Amenger, Gbaden as an original project investigator is supplied in the journal editorial authorship information for this paper and is not independently visible on the archived title/certification pages reviewed for e049. Study type: Theoretical engineering review and mathematical re-analysis; no new hardware dataset is claimed. Funding: No external research funding is documented in the archived project. Competing interests: None declared. Data/materials boundary: Numerical values identified as archived are taken from the 2016 project record. New values in e049 are equation-derived re-analysis using those archived parameters and are not represented as newly measured results. Ethics: Not applicable; no human or animal participants are involved.

Author Contributions (CRediT-style)

References

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