CHIATECH JOURNAL · HTML Version of Record

Loss-Aware Reliability Analysis and Contemporary Re-Engineering of a 24 V-to-19 V, 66.5 W PWM Buck Converter: Component Stress, Efficiency Bounds and Validation Protocol

1. Shiaondo Kenneth Chia
2. Gbaden Amenger
3. N. Y. Goshwe

Volume 1, Issue 2 · Pioneer Volume · August 2026 · Part 2 · e048 · ISSN pending assignment

CHIATECH JOURNAL

SETEHEM · Volume 1, Issue 2 · Pioneer Volume · August 2026 · Part 2 · e048

PIONEER PUBLICATION · ACCEPTED ARTICLE · ORIGINAL ENGINEERING RESEARCH · POWER ELECTRONICS · RELIABILITY · ENERGY EFFICIENCY

Loss-Aware Reliability Analysis and Contemporary Re-Engineering of a 24 V-to-19 V, 66.5 W PWM Buck Converter: Component Stress, Efficiency Bounds and Validation Protocol

CHIA, Shiaondo Kenneth¹* · AMENGER, Gbaden² · GOSHWE, N. Y.³

¹ CHIA TECH Solutions and Resources Limited, Nigeria; original project investigator, Department of Electrical/Electronic Engineering, Federal University of Agriculture Makurdi (2016)

² Nigeria Customs Service, Ogun State Command, Nigeria; original project investigator, Department of Electrical/Electronic Engineering, Federal University of Agriculture Makurdi (2016)

³ Department of Electrical/Electronic Engineering, Federal University of Agriculture Makurdi, Nigeria; project supervisor (2016)

*Corresponding author: chiakenneth01@gmail.com · ORCID: https://orcid.org/0009-0009-6434-4586

Abstract

Background: The archived 2016 project developed a 24 V-to-19 V pulse-width-modulated buck converter at 30 kHz with a 3.5 A, 66.5 W rated point, a 251 µH inductor, 15 µF output capacitor, 10 mΩ capacitor ESR and 2 mΩ inductor DCR. The report documents MATLAB/Simulink development, PWM waveforms and prototype implementation, and later states efficiency above 81%, but it does not preserve a complete part-specific loss budget or a traceable efficiency-test boundary. Objective: This study performs a distinct reliability-oriented re-analysis of the same engineering work, quantifying component current stress, reconstructable passive losses, semiconductor-loss sensitivity and the measurement requirements needed for a modern repeat build. Methods: Source parameters were preserved exactly. Continuous-conduction-mode equations were used to derive peak/RMS currents and ripple. Because MOSFET RDS(on), diode forward drop and switching transition times are not recoverable from the archive, they were treated as explicit sensitivity variables rather than invented historical measurements. Parametric efficiency surfaces and load sweeps were generated from transparent analytical assumptions. Results: The rated duty ratio is 0.7917 and the inductor ripple is 0.526 A p-p, giving Ipk = 3.763 A, IQ,rms = 3.117 A, ID,rms = 1.599 A and IC,rms = 0.152 A. The documented 2 mΩ inductor DCR contributes only about 24.55 mW copper loss and the 10 mΩ capacitor ESR about 0.23 mW at the rated point. Incremental loss sensitivity is approximately 0.097 W per additional 10 mΩ of MOSFET RDS(on), 0.073 W per 0.1 V of diode forward drop and 0.0126 W per additional 10 ns of combined switching transition. Even a deliberately conservative analytical stress case remains above 96% when only these modeled power-stage terms are included; therefore, the archived “>81%” statement cannot be reconstructed from the available component record alone. At 66.5 W output, exactly 81% efficiency would correspond to a 15.60 W total-loss ceiling, but the historical measurement boundary is unspecified. Conclusion: The design is a strong educational and engineering case study, but a contemporary efficiency or reliability claim should be based on a fresh parts audit, simultaneous input/output power measurement, loop-gain verification, calibrated ripple capture and thermal characterization. The paper preserves the historical prototype evidence while preventing analytical reconstructions from being misreported as new measurements.

Keywords: buck converter; power loss; efficiency; component stress; reliability; thermal design; PWM; DC-DC conversion; failure-mode analysis; validation protocol

1. Introduction

Efficiency in a switching converter is not a single-component property; it emerges from conduction loss, switching overlap, magnetic loss, diode or synchronous-rectifier loss, capacitor ESR, gate-drive consumption, layout parasitics and the thermal state of the semiconductor devices. Modern power-stage guidance therefore couples current stress, component ratings and heat dissipation to the same equations used for voltage and ripple design (Hauke, 2015; Analog Devices, n.d.). Recent research likewise treats power loss and thermal behavior as reliability variables rather than as secondary reporting items (Alavi et al., 2022; Yang et al., 2024).

The project underlying e048 was originally designed around a 24 V input, 19 V regulated output, 3.5 A rated load and 30 kHz switching frequency. It used voltage-mode PWM with Type-III compensation and documented both simulation and practical construction. A separate e046 article focused on power-stage mathematics, small-signal modeling and compensation. The present e048 paper is deliberately different: it asks what can—and cannot—be said about loss, component stress, thermal risk and reliability using only the archived evidence plus transparent analytical sensitivity models.

Figure 1. Loss-aware engineering architecture used in e048. The documented L, C, ESR and DCR remain source-derived; semiconductor loss parameters are treated only as variables because the archive does not preserve a verified final part set with complete electrical characteristics.

1.1 Evidence boundary and research questions

The article addresses four questions: (1) what current and ripple stresses follow directly from the archived design point; (2) how large are the losses that can be reconstructed from documented passive parameters; (3) how sensitive is predicted efficiency to semiconductor parameters that are absent from the source; and (4) what measurement protocol is required before a future rebuild can make defensible claims about efficiency, temperature and lifetime. This approach follows the principle that historical evidence, analytical derivation and new measurement must remain visibly distinct.

2. Source Parameters and Analytical Method

Table 1. Source-constrained baseline used in e048. No new part number, oscilloscope scale or measured efficiency point is inferred from these values.

2.1 Duty ratio and current ripple

For an ideal buck converter in CCM, the steady-state duty ratio follows volt-second balance:

The peak-to-peak inductor current ripple is

The resulting current extrema and RMS inductor current are

2.2 Switch, diode and capacitor RMS stress

Neglecting turn-on/turn-off overlap for the RMS-current calculation, the high-side switch conducts during D and the freewheel diode during 1−D:

For approximately triangular ripple current, the output-capacitor RMS current is

Figure 2. Rated-point current stress derived from the archived power-stage parameters. The MOSFET and diode waveforms are idealized CCM conduction windows, useful for rating and loss analysis but not substitutes for oscilloscope current-probe measurements.

Figure 3. Rated-point stress dashboard. Passive losses shown here are directly reconstructable from the documented DCR and ESR; device-specific conduction and switching losses are not.

2.3 Reconstructable passive losses

The documented inductor DCR yields a copper-loss term

and the output-capacitor ESR yields

These values exclude inductor core loss, high-frequency winding effects, capacitor dielectric loss and layout parasitics. Their purpose is to define the minimum part of the loss budget that can be calculated from the archive, not to imply that the historical converter dissipated only these amounts.

2.4 Parametric semiconductor-loss model

Because the archived record does not preserve a complete verified MOSFET/diode data sheet set, e048 uses the standard analytical forms below as sensitivity equations. The model follows contemporary buck loss practice in which RMS conduction current, device voltage drop and switching transition overlap are treated explicitly (Texas Instruments, 2020; Yang et al., 2024).

The explicit residual term Pother is essential. It contains gate-drive power, diode recovery, MOSFET output-capacitance loss, inductor core loss, interconnect loss, control-circuit consumption and any upstream 24 V source-chain loss that was included in the original measurement boundary.

3. Results: Loss Sensitivity and Efficiency Bounds

3.1 First-order sensitivity coefficients

Table 2. Rated-point first-order loss sensitivities. These coefficients are more reproducible than assigning an unverified historical device part number.

Figure 4. Incremental loss sensitivity. At the archived operating point, diode forward drop and MOSFET on-resistance matter far more to the loss budget than the documented 10 mΩ output-capacitor ESR.

3.2 Parametric efficiency envelope

To visualize the uncertainty introduced by missing semiconductor data, RDS(on) was swept from 10 to 100 mΩ and diode forward drop from 0.35 to 0.95 V while combined switching transition time was fixed at 100 ns. These ranges are deliberately broad engineering sensitivity bounds, not claims about the actual 2016 devices.

Figure 5. Parametric efficiency surface at the 66.5 W rated point. The heat map includes only the loss terms explicitly stated in Equation (12) except Pother, so it should be interpreted as a bounded analytical envelope rather than a prototype efficiency map.

3.3 Load dependence under three transparent scenarios

Three illustrative scenarios were defined to show how loss terms redistribute as load changes: low-loss (15 mΩ, 0.35 V, 60 ns), moderate (50 mΩ, 0.60 V, 120 ns) and stress case (100 mΩ, 0.95 V, 300 ns). All use the same archived L, C, ESR and DCR. None is asserted to be the historical final component set.

Figure 6. Analytical efficiency-versus-load sensitivity. The model remains in CCM over the plotted 0.5–3.5 A range because the reconstructed ripple half-amplitude is approximately 0.263 A.

3.4 Audit of the archived “>81%” statement

The source conclusion states that the implemented converter operated with power efficiency higher than 81% and gives a settling-time statement, but it does not provide a complete measurement table, instrument accuracy, input-power boundary or final component data from which the efficiency can be recomputed. At exactly 81% efficiency and 66.5 W output, the implied total loss would be 15.60 W. Since the source says “higher than 81%,” the true historical loss—if measured at the same 66.5 W point—would be lower than this ceiling, but its exact value remains unknown.

Figure 7. Loss-budget audit. The large separation between reconstructable power-stage terms and the 81% efficiency floor demonstrates why the historical efficiency value should not be “corrected” by assumption; the measurement boundary and omitted loss mechanisms must first be recovered or re-measured.

4. Historical Simulation Evidence and Publication Boundary

The archived report contains a MATLAB/Simulink converter model, PWM traces and output/load waveforms, and it describes practical implementation. These materials establish that the design was not purely conceptual. However, the available figures are insufficient to recover calibrated efficiency, thermal or component-stress data because the axes, instrumentation and test conditions needed for those claims are not fully preserved. e048 therefore reproduces the historical evidence only as provenance and builds new calculations from explicitly stated equations.

Figure 8. Selected archived 2016 simulation evidence from the project file: MATLAB/Simulink model, PWM waveform and output/load waveform. These images are retained as historical evidence and are not redrawn as if they were new 2026 measurements.

5. Reliability-Oriented Re-Engineering

5.1 Electrical stress and component rating

A contemporary rebuild should rate the high-side MOSFET above the 24 V bus with transient margin, select continuous and pulsed current ratings above the 3.763 A reconstructed peak, and verify RDS(on) at the expected junction temperature rather than using only a 25 °C data-sheet number. The freewheel diode should be rated for reverse voltage above the input bus and for average/RMS current at the off-state duty fraction. The archived project’s component table and design narrative contain inconsistent diode naming; e048 therefore does not assign a definitive legacy diode part number.

5.2 Thermal reliability

Power-converter reliability is strongly coupled to semiconductor temperature. The basic thermal relation is

but neither the actual package thermal resistance nor the measured case/junction temperature is available in the archived project. Consequently, e048 reports no historical junction temperature. Instead, a new build should record ambient temperature, board construction, copper area, airflow, device case temperature and the thermal-resistance model used to infer junction temperature. This is consistent with reliability literature that treats junction-temperature cycling and thermal stress as major lifetime determinants in power electronic converters (Alavi et al., 2022).

5.3 Failure-mode and verification matrix

Table 3. Reliability and validation matrix. The table converts uncertainties in the historical record into concrete measurements for a future repeat build.

5.4 Synchronous-rectification upgrade pathway

The archived converter uses a freewheel diode. A contemporary high-efficiency redesign can replace the diode with a controlled low-side MOSFET, reducing off-state conduction loss from approximately (1−D)IoVF to (1−D)IL,rms²RDS(on,LS), subject to dead-time and reverse-recovery/body-diode effects. This is an upgrade pathway rather than a retroactive claim about the 2016 circuit. Modern wide-bandgap devices and digital control can further improve switching speed and transient response, but these technologies require a new design and verification cycle rather than a simple part substitution (Kroičs et al., 2024).

6. Contemporary Validation Protocol

A repeat build intended for publication should use a pre-declared test matrix. At minimum: (i) identify final part numbers and data-sheet revisions; (ii) sweep load from light load to rated load while logging input voltage/current and output voltage/current simultaneously; (iii) state whether efficiency is measured from the 24 V DC input or from the upstream 230 V AC source; (iv) capture ripple using a defined bandwidth limit and low-inductance probing; (v) measure loop gain/phase rather than inferring stability from time-domain plots alone; (vi) record ambient and device temperatures; and (vii) publish raw CSV data, scope settings, BOM and calculation scripts. Recent Type-III buck-converter work reinforces the value of validating dynamic performance over operating conditions rather than relying on a single nominal simulation (Huang & Lian, 2024).

Figure 9. Rebuild-and-validate chain for future experimental publication. This workflow would convert the present historical/analytical case study into a fully reproducible modern hardware dataset.

7. Discussion

The most important result of e048 is not an efficiency number; it is a defensible loss boundary. The archived passive values produce very small reconstructable dissipation at the rated point, while semiconductor conduction and switching losses depend on component properties that are not recoverable with confidence. This is exactly the situation in which an academic article should use a parametric model instead of silently choosing convenient part characteristics. The resulting sensitivity analysis shows why diode forward drop, MOSFET on-resistance and switching transition time dominate the known uncertainty at 30 kHz.

The analysis also clarifies why a historical “>81%” efficiency statement can coexist with a power-stage model that predicts substantially higher efficiency under plausible semiconductor assumptions: the original measurement boundary may have included upstream conversion losses, magnetic/core loss, drive/control consumption, wiring and contact resistance, nonideal device characteristics or measurement uncertainty. The source does not preserve enough information to rank these explanations. Therefore e048 does not reinterpret the archived efficiency as false; it classifies it as non-reconstructable from the surviving record.

Finally, the paper strengthens the educational value of the original project. The same 24 V-to-19 V converter can be used to teach duty-cycle design, CCM ripple, RMS device rating, power-loss partitioning, thermal resistance, efficiency measurement and reliability engineering as one connected workflow. This integrated treatment is more representative of professional power-electronics practice than a design that ends at schematic simulation.

8. Conclusion

The archived 24 V-to-19 V, 66.5 W PWM buck converter remains technically valuable as a historical design-and-build project. Source-constrained analysis gives D = 0.7917, ΔIL = 0.526 A p-p, Ipk = 3.763 A, IQ,rms = 3.117 A and ID,rms = 1.599 A. The documented 2 mΩ inductor DCR contributes only 24.55 mW at rated load and the 10 mΩ output-capacitor ESR only 0.230 mW, so the historical efficiency cannot be reconstructed without semiconductor, magnetic, control and measurement-boundary data. e048 therefore makes a stronger claim than an invented efficiency curve: it establishes a transparent mathematical stress/loss model, quantifies the sensitivity to missing device parameters, identifies the evidentiary limit of the 2016 record and defines a reproducible protocol for a modern repeat build. This approach preserves the genuine project evidence while meeting contemporary expectations for traceability, reliability and engineering publication quality.

Declarations

Authorship/provenance: Author identities and project-role attributions are presented according to the editorial information supplied for e048. The archived project file reviewed for this article independently contains the 2016 buck-converter design record and identifies Chia S. Kenneth on the title/certification pages and Goshwe N. Y. in the supervisory role. Funding: No external research funding is documented in the archived project. Competing interests: None declared. Data and materials: The historical evidence is the archived 2016 project report and its embedded simulation figures. All new numerical values in e048 are equation-derived or explicitly labeled parametric sensitivity scenarios. No new hardware efficiency, oscilloscope or thermal dataset is claimed. Ethics: Not applicable; the study concerns an electrical power-conversion system and contains no human or animal participants.

Author Contributions (CRediT-style)

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