CHIATECH JOURNAL · HTML Version of Record

Design, Small-Signal Modeling and Prototype Implementation of a 24 V-to-19 V PWM Buck Converter with Type-III Voltage-Mode Compensation

1. Shiaondo Kenneth Chia
2. Gbaden Amenger
3. N. Y. Goshwe

Volume 1, Issue 2 · Pioneer Volume · August 2026 · Part 2 · e046 · ISSN pending assignment

CHIATECH JOURNAL

SETEHEM · Volume 1, Issue 2 · Pioneer Volume · August 2026 · Part 2 · e046

PIONEER PUBLICATION · ACCEPTED ARTICLE · ORIGINAL ENGINEERING RESEARCH · ELECTRICAL/ELECTRONIC ENGINEERING · POWER ELECTRONICS · CONTROL SYSTEMS

Design, Small-Signal Modeling and Prototype Implementation of a 24 V-to-19 V PWM Buck Converter with Type-III Voltage-Mode Compensation

CHIA, Shiaondo Kenneth¹*. AMENGER, Gbaden2

GOSHWE, N. Y.3

¹ CHIA TECH Solutions and Resources Limited, Nigeria; original project investigator, Department of Electrical/Electronic Engineering, Federal University of Agriculture Makurdi (2016)

2Nigeria Customs Service, Ogun State Command, Nigeria. original project investigator, Department of Electrical/Electronic Engineering, Federal University of Agriculture Makurdi (2016)

3Department of Electrical/Electronic Engineering, Federal University of Agriculture Makurdi, Nigeria; project supervisor (2016)

*Corresponding author: chiakenneth01@gmail.com · ORCID: https://orcid.org/0009-0009-6434-4586

Abstract

Background: A 2016 engineering project at the Federal University of Agriculture Makurdi designed and implemented a pulse-width-modulated buck converter to step 24 V DC down to a regulated 19 V output. Objective: This article converts that archived project into a compact, publication-ready engineering paper, reconstructing the power-stage mathematics, voltage-mode feedback loop and Type-III compensation while preserving the documented prototype and simulation evidence. Methods: The archived specifications were audited and re-expressed using continuous-conduction-mode (CCM) equations, small-signal control-to-output modeling, K-factor pole-zero placement and analytical ripple calculations. The source specifies 24 V input, 19 V rated output, 3.5 A, 66.5 W, 30 kHz switching, L = 251 µH, C = 15 µF, capacitor ESR = 10 mΩ and inductor DCR = 2 mΩ. Results: The ideal duty ratio is 0.7917. At the 3.5 A design point the equivalent rated load is 5.43 Ω, while the archived simulation schematic separately uses a nominal 5 Ω test load. The reconstructed inductor ripple is approximately 0.526 A peak-to-peak (15.0% of rated output current), with an analytical output-ripple estimate of about 0.151 V peak-to-peak when capacitive and ESR terms are combined. The LC double-pole frequency is approximately 2.594 kHz and the capacitor-ESR zero approximately 1.061 MHz. The documented Type-III network (R1 = 2.2 kΩ, R2 = 5.9 kΩ, R3 = 38.8 Ω, C1 = 34.2 nF, C2 = 0.6 nF, C3 = 90 nF) is consistent with a voltage-mode compensation strategy that places two zeros around the LC resonance and high-frequency poles above the crossover region. Conclusion: The archived design is technically coherent at its rated point and demonstrates the engineering value of PWM, CCM energy transfer and Type-III loop shaping. The article also identifies legacy reporting inconsistencies that should not be interpreted as new measurements, notably the source wording that labels 19 V and 3.5 A as ripple values.

Keywords: buck converter; DC-DC conversion; pulse-width modulation; voltage-mode control; Type-III compensation; K-factor; small-signal model; continuous conduction mode; power electronics

1. Introduction

Switch-mode DC-DC converters regulate voltage by transferring energy through controlled switching rather than dissipating the excess voltage as heat. In the buck topology, a high-side switch, freewheeling path, inductor and output capacitor form a second-order power stage whose average output is controlled primarily through duty ratio. Modern design guidance continues to treat the inductor-current ripple, output-capacitor ESR, switching frequency and control-loop bandwidth as coupled design variables (Hauke, 2015; Analog Devices, n.d.-a). The archived project that forms the evidence base for this article was completed in April 2016 by Chia S. Kenneth under the supervision of Goshwe N. Y. It targeted a 24 V-to-19 V PWM converter, used voltage feedback and Type-III compensation, and reported both simulation and Vero-board implementation.

Figure 1. Reconstructed system architecture of the archived PWM buck converter. The original project describes a voltage-feedback loop in which the measured output is compared with a 19 V reference, compensated, converted to PWM by a sawtooth comparator and applied to the MOSFET through a gate driver.

1.1 Contribution and evidence provenance

The contribution of e046 is not to relabel a 2016 student project as a new 2026 experiment. Instead, it performs a transparent engineering reconstruction: it preserves the documented design parameters and implementation claims, rewrites the mathematics in a traceable form, derives quantities that follow directly from the documented parameters, and separates those analytical reconstructions from measurements that cannot be independently recovered from the archived plots. This distinction is important because the report contains several legacy notation and unit inconsistencies. The journal version resolves such issues explicitly rather than silently replacing the source record.

Figure 2. Evidence provenance and reproducibility boundary used for e046. Derived quantities are identified as analytical reconstruction; the article does not invent oscilloscope scales or new prototype measurements.

2. Buck-Converter Theory and Voltage-Mode Control

2.1 Ideal conversion ratio and switching interval

For an ideal buck converter operating in CCM, volt-second balance on the inductor gives the familiar conversion ratio

Thus the rated duty ratio for 24 V to 19 V conversion is

Figure 3. Power-stage states. During Q1 ON-time the source charges the inductor and supplies the load; during OFF-time the diode provides a current path so that inductor current remains continuous.

2.2 Inductor-current ripple and CCM condition

During the ON interval, the ideal inductor voltage is Vin − Vo; during the OFF interval it is approximately −Vo. The peak-to-peak current ripple is therefore

At the 3.5 A rated operating point, the reconstructed current range is approximately 3.237 to 3.763 A. Because the minimum remains well above zero, the rated point is unambiguously in CCM.

2.3 Output-capacitor ripple

For a triangular capacitor current in CCM, a common first-order ripple estimate is the sum of the capacitive charging term and the capacitor-ESR term:

2.4 Voltage-mode PWM control

The project uses a single outer voltage loop. The output-voltage error is amplified and shaped by the compensator; the resulting control voltage is compared with a fixed-frequency sawtooth to generate the gate PWM. This is the conventional voltage-mode architecture described in contemporary control-loop guidance, in which the LC double pole introduces up to −180° phase shift and usually motivates Type-III compensation when a wider bandwidth is desired (Analog Devices, n.d.-a, n.d.-b).

Figure 4. PWM timing at the rated ideal duty ratio. The 2 V sawtooth level is included as a reconstruction because the archived Type-III component table contains a 2 V modulation quantity; the exact original comparator scale is not independently recoverable from the source plots.

3. Design Reconstruction

3.1 Archived specifications and source reconciliation

Table 1. Design specification and reconciliation. The 5.43 Ω rated equivalent load and the archived 5 Ω simulation load are not treated as the same condition.

Figure 5. Rated-point engineering quantities derived from the documented design parameters.

3.2 Power, load and switch stress

For the ideal design point, the MOSFET must conduct approximately the inductor current during D·Ts and block approximately Vin during OFF-time; the freewheeling diode carries the inductor current during (1−D)·Ts. Practical device selection therefore requires voltage margin above 24 V, current margin above the reconstructed peak current, low conduction loss and switching performance compatible with 30 kHz. The archived schematic identifies Q1 as a MOSFET and lists a 3 A diode selection in the design narrative, while another component table identifies an IN4141-type device. That naming inconsistency is retained as a source limitation; e046 does not substitute a specific modern part number without a new hardware audit.

3.3 Output filter frequencies

The undamped LC natural frequency and the capacitor-ESR zero are

The source report independently states an output-filter double-pole frequency of 2.594 kHz, which agrees closely with the reconstruction above. Because the ESR zero is far above the LC resonance, the capacitor does not provide useful phase lead near crossover; this supports the documented choice of Type-III compensation.

3.4 Type-III compensation and K-factor interpretation

A Type-III compensator contributes one pole at the origin, two finite zeros and two high-frequency poles. A convenient generic form is

The archived project uses a K-factor design and reports a required phase boost of approximately 150°. For the common Type-III K-factor relation

This reproduces the archived reported K-factor of about 57.7. The source component set is listed below.

Figure 6. Clean Type-III network reconstruction and the design pole-zero placement used for the analytical loop model. Exact original op-amp parasitics are not modeled.

4. Analytical Results and Comparison with Archived Evidence

4.1 Rated-point ripple and CCM behavior

Figure 7. Analytical rated-point ripple. These are reconstructed theoretical waveforms from the documented L, C, ESR, fs, Vin and Vo; they are not digitized measurements from the archived MATLAB figure.

The reconstructed inductor ripple of 0.526 A p-p is exactly 15.0% of the rated 3.5 A current, closely matching the project design target of 15% current ripple. The corresponding output-voltage ripple estimate is about 0.151 V p-p, or 0.80% of the 19 V output. This distinction matters because the archived report states that the “measured ripple” values are 19 V and 3.5 A; those numbers coincide with the output-voltage and rated-current levels rather than plausible ripple amplitudes. e046 therefore treats that wording as a legacy reporting error and does not reproduce it as a ripple measurement.

4.2 Small-signal power-stage model

For an approximate voltage-mode analysis that retains capacitor ESR but neglects detailed switch, diode, op-amp and layout parasitics, the control-to-output plant can be represented as

The Type-III zeros were placed around one-half of f0 and f0, with a high-frequency pole near fs/2 and another near the capacitor-ESR zero. The compensator gain was normalized so that the open-loop magnitude crosses 0 dB near 6 kHz (approximately fs/5), consistent with the archived design narrative that crossover should remain well below the switching frequency.

Figure 8. Analytical Bode reconstruction. With the stated pole-zero placement and normalization, the loop crosses near 6 kHz with an indicative phase margin of about 54.5°. This plot is an e046 analytical reconstruction, not a claim that the original archived MATLAB Bode trace had exactly these numerical coordinates.

4.3 Archived simulation and prototype evidence

The source report documents a full Proteus-style schematic, a MATLAB/Simulink converter model, PWM waveforms, output-voltage/load-current plots and implementation first on a breadboard and then on Vero board. It concludes that the converter produced the 19 V target from 24 V at 30 kHz and reports efficiency above 81% together with a 0.5 s settling-time statement. However, the archived pages available for this publication do not provide a traceable efficiency table, calibrated oscilloscope scales or a complete load sweep from which those two performance claims can be independently recomputed. Accordingly, they are retained as archived project observations rather than elevated to newly verified 2026 measurements.

5. Discussion

5.1 What the design demonstrates

First, the power-stage sizing is internally coherent at the central design point: the 79.17% duty ratio follows directly from the target voltage ratio, and the 251 µH inductor produces almost exactly the intended 15% current ripple at 30 kHz. Second, the 15 µF capacitor with 10 mΩ ESR gives a sub-1% first-order output-ripple estimate at rated current, illustrating how capacitor selection and ESR jointly shape both ripple and loop dynamics. Third, the LC resonance near 2.6 kHz is close enough to the intended control bandwidth that simple integral compensation would be inadequate for a fast voltage-mode loop; Type III is therefore a technically defensible choice. This agrees with modern guidance that voltage-mode buck converters frequently require two compensating zeros around the LC resonance and high-frequency poles to preserve phase margin while attenuating switching noise (Analog Devices, n.d.-a; Texas Instruments, 2010).

5.2 Source inconsistencies and how e046 handles them

Table 2. Transparent treatment of legacy reporting inconsistencies. No unsupported correction is presented as if it were an original measurement.

5.3 Engineering upgrades for a contemporary re-build

A new build should retain the topology-learning value of the project while improving measurement traceability and protection. Recommended upgrades are: (i) use a modern low-RDS(on) MOSFET and a diode/synchronous rectifier with documented voltage/current margin; (ii) add input and output decoupling close to the switching loop; (iii) measure loop gain with a frequency-response analyzer or injection method rather than relying only on simulation; (iv) record output ripple with bandwidth-limited differential probing and clearly stated probe ground technique; (v) log input power and output power simultaneously to produce an efficiency curve versus load; (vi) quantify startup overshoot and settling time against a defined tolerance band; and (vii) use current limiting, over-voltage protection, thermal sensing and controlled dead time where appropriate. Modern vendor guidance also recommends verifying the calculated loop against time-domain load transients and component tolerances rather than treating a nominal Bode plot as sufficient by itself (Analog Devices, n.d.-b).

6. Conclusion

The 24 V-to-19 V PWM buck converter project is a defensible foundation for a technical journal article when its historical evidence and its modern analytical reconstruction are clearly separated. The core design is mathematically consistent: D ≈ 0.7917, Pout = 66.5 W at 3.5 A, the 251 µH inductor yields about 0.526 A p-p ripple at 30 kHz, and the LC resonance is approximately 2.594 kHz. The documented Type-III network and K-factor of about 57.7 are consistent with the need for substantial phase boost in voltage-mode control. The original project further documents MATLAB/Simulink and Proteus-based development and a Vero-board implementation that achieved the 19 V target. The most important publication improvement in e046 is evidentiary discipline: analytical results are explicitly labeled, legacy inconsistencies are exposed rather than hidden, and no new bench precision is invented from uncalibrated historical plots.

Declarations

Authorship/provenance: The archived project identifies CHIA S. KENNETH as the student investigator and ENGR. DR. GOSHWE N. Y. as supervisor. e046 presents these two project contributors as authors following editorial instruction; the 2016 role labels are preserved transparently. Funding: No external funding is documented in the archived project. Competing interests: None declared. Data and materials: The article is derived from the archived project report and its embedded schematics/simulation figures. No new raw oscilloscope or efficiency dataset is claimed. Ethics: Not applicable; the work concerns an electrical power-conversion prototype and contains no human or animal participants.

Author Contributions (CRediT-style)

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